1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device comprising a MIS field-effect transistor and a semiconductor device comprising a MIS field-effect transistor that is fabricated by that method.
2. Description of Related Art
Various methods of fabricating a metal-insulator semiconductor (MIS) field-effect transistor have been disclosed, such as that in Japanese Patent Application Laid-Open No. 9-162402, for example. The method of fabricating an MIS field-effect transistor disclosed in that document will be descried below.
A p-type well 202 is formed on the main surface of a p-type silicon substrate 200, as shown in FIG. 40. A field oxide layer 204 is formed around the p-type well 202, to separate the elements. A gate oxide layer 206 is formed on the p-type well 202. A polysilicon layer 208 is formed on the gate oxide layer 206.
The polysilicon layer 208 is etched selectively to form a gate electrode 212, as shown in FIG. 41. The gate electrode 212 and the field oxide layer 204 are used as a mask for the implantation of ions of arsenic into the main surface of the silicon substrate 200, to form nxe2x88x92-type regions 214. A chemical vapor deposition (CVD) method is then used to form a silicon nitride layer 210 on the main surface of the silicon substrate 200 in such a manner as to cover the gate electrode 212. Anisotropic etching is used to etch back this silicon nitride layer 210 so that the remaining silicon nitride layer 210 has a thickness of 10 nm and shields the side surfaces of the gate electrode 212 and the side surfaces of the gate oxide layer 206. The formation of the silicon nitride layer 210 at positions shielding the side surfaces of the gate oxide layer 206 ensures that the supply of oxygen to the gate oxide layer 206 is prevented. This prevents the occurrence of xe2x80x9cbird""s beakxe2x80x9d in the gate oxide layer 206 of the gate. Gate bird""s beak is a cause of deterioration of the characteristics of the MIS field-effect transistor. The thickness of the silicon nitride layer 210 is set to 10 nm for reasons given below. A source/drain of the resultant MIS field-effect transistor consists of three regions: an nxe2x88x92-type region, an n-type region, and an n+-type region. The nxe2x88x92-type region is positioned below the silicon nitride layer 210. If the thickness of the silicon nitride layer 210 is less than 10 nm, the width of the nxe2x88x92-type region is also less than 10 nm. If the width of the nxe2x88x92-type region is less than 10 nm, the nxe2x88x92-type region becomes absorbed into the neighboring n-type region and it can no longer function as an nxe2x88x92-type region.
The gate electrode 212, the silicon nitride layer 210, and the field oxide layer 204 are used as a mask for the implantation of arsenic ions into the main surface of the silicon substrate 200, to form n-type regions 218 as shown in FIG. 42. A silicon oxide layer is then formed on the main surface of the silicon substrate 200 by a CVD method, to cover the gate electrode 212. This silicon oxide layer is etched back by using anisotropic etching to form a side-wall silicon oxide layer 216 in such a manner that it shields the silicon nitride layer 210.
The gate electrode 212, the silicon nitride layer 210, the side-wall silicon oxide layer 216, and the field oxide layer 204 are used as a mask for the implantation of arsenic ions into the main surface of the silicon substrate 200, to form n+-type regions 220 as shown in FIG. 43.
An intermediary insulation layer 222 is formed over the entire surface of the silicon substrate 200 so as to cover the gate electrode 212, as shown in FIG. 44. Contact holes 224 are formed in the intermediary insulation layer 222 to reach the n+-type regions 220. A conductive layer is formed on top of the intermediary insulation layer 222 and within the contact holes 224. A wiring layer 226 is formed by subjecting this conductive layer to given patterning. The MIS field-effect transistor is fabricated by the above steps.
Referring back to FIG. 41, the nxe2x88x92-type regions 214 are formed by the implantation of ions into the main surface of the silicon substrate 200, using the gate electrode 212 as a mask. The side surfaces of the gate oxide layer 206 are exposed during this ion implantation. Since the side surfaces of the gate oxide layer 206 are exposed, ions strike the side surfaces of the gate oxide layer 206. This results in places at edge portions of the gate oxide layer 206 where the bonding of the crystalline structure of the gate oxide layer are broken. There are three main problems caused by breakage of the bonding of the crystalline structure in the gate oxide layer: the dielectric breakdown voltage drops at the places in the gate insulation layer where the crystalline structure is damaged, so the dielectric breakdown voltage of the entire gate insulation layer drops; carriers flow through the places in the gate insulation layer where the crystalline structure is damaged, causing a leakage current through the gate insulation layer; and carriers flowing through the channel can easily be trapped at the places in the gate insulation layer where the crystalline structure is damaged. These all change the characteristics of the MIS field-effect transistor. The long-term reliability of the MIS field-effect transistor also falls.
If tilted ion implantation 258 in particular is used to form a source/drain 254, as shown in FIG. 45, a large number of ions will strike the side surfaces of the gate oxide layer 206 directly. This makes it more likely for large numbers of places where the bonding of the crystalline structure are broken to appear in the edge portions of the gate oxide layer 206. The reasons for using tilted ion implantation will now be discussed. If this tilted ion implantation 258 is used to create the source/drain 254, edge portions 256 of the source/drain 254 are formed at positions overlapping the gate electrode 212. This will prevent carriers that are flowing through the channel from jumping into the gate oxide layer 206. In other words, if a side surface of one of the nxe2x88x92-type regions 214 of the source or drain is positioned directly below a side surface of the gate electrode 212, concentrations in electrical field will occur at the places indicated by arrows A. These electrical field concentrations make it easy for the carriers flowing in the channel to jump into the gate oxide layer 206. If carriers jump into the gate oxide layer 206, the characteristics of the gate oxide layer 206 will deteriorate.
Note that the nxe2x88x92-type regions 214 shown in FIG. 41 could also be formed by diffusion. The side surfaces of the gate oxide layer 206 will still be exposed, even when the nxe2x88x92-type regions 214 are formed by diffusion. This means that the diffused impurity will go through the side surfaces of the gate oxide layer 206 into the crystalline structure of the gate oxide layer 206. This will cause the dielectric breakdown voltage of the gate oxide layer 206 to drop.
With the fabrication of a MIS field-effect transistor, a silicide layer is often formed on the upper surface of the gate electrode, to lower the electrical resistance of the gate electrode. This is discussed below.
A p-type well 232 is formed in a main surface of a p-type silicon substrate 230, as shown in FIG. 46. A field oxide layer 234 is formed around the p-type well 232. A gate oxide layer 236 and a polysilicon layer are then formed on the main surface of the silicon substrate 230. A gate electrode 238 is then formed by subjecting the polysilicon layer to given patterning. The gate electrode 238 and the field oxide layer 234 are used as a mask for the implantations of ions into the main surface of the silicon substrate 230, to form nxe2x88x92-type regions 242. A silicon oxide layer is then formed on the main surface of the silicon substrate 230 so as to cover the gate electrode 238. This silicon oxide layer is etched back by anisotropic etching to form a side-wall silicon oxide layer 240 that shields the side surfaces of the gate electrode 238 and the gate oxide layer 236. For example, the side-wall silicon oxide layer 240 is over-etched to ensure that none of the silicon oxide layer remains at stepped portions, such as that indicated by A in the FIG. 46. This means that the remaining side-wall silicon oxide layer 240 is positioned lower than corner portions 260 formed by side surfaces and the upper surface of the gate electrode 238. The gate electrode 238, the side-wall silicon oxide layer 240, and the field oxide layer 234 are then used as a mask for the implantation of ions into the main surface of the silicon substrate 230, to form n+-type regions 244.
Using a method such as sputtering, a titanium layer 246 is formed over the entire main surface of the silicon substrate 230, as shown in FIG. 47.
The titanium layer 246 is subjected to thermal treatment to cause the titanium layer that is positioned on top of the upper surface of the gate electrode 238 and above the n+-type regions 244 to react with the silicon and thus form titanium silicide layers 248 and 250, as shown in FIG. 48. The side surfaces of the gate electrode 238 are exposed at the corner portions 260 of the gate electrode 238. This means that silicon is supplied to the titanium layer from these portions as well, during the formation of the titanium silicide layer. The result of supplying silicon from the upper and side surfaces of the gate electrode 238 at the corner portions 260 of the gate electrode 238 is an excess of silicon reacting with the titanium layer, so that the thickness of edge portions 262 of the resultant titanium silicide layer 248 is greater than that of a central portion 263 thereof.
The unreacted titanium layer on top of the field oxide layer 234 and the side-wall silicon oxide layer 240 is removed, as shown in FIG. 49.
Using a method such as CVD, an intermediary insulation layer 252 is then formed over the entire main surface of the silicon substrate 230, as shown in FIG. 50. Protuberant portions 266 are inevitably formed in the intermediary insulation layer 252, to reflect the increased thickness of the edge portions 262 of the titanium silicide layer 248. When the gate electrode pattern and the wiring pattern become finer in the future, it is possible that the wiring layer will break if it is formed on top of such protuberant portions 266. If the silicide layer is too thick, furthermore, the thermal stresses generated in the silicide layer will also be greater than when the film is thinner. If the thickness of the edge portions of the silicide layer increases, the thermal stresses in those portions of the silicide layer will increase. This means that the thermal stresses imposed on the gate insulation layer from the silicide layer will also increase. This will lead to changes in the characteristics of the MIS field-effect transistor and a deterioration in its long-term reliability.
Problems will occur even if the side-wall silicon oxide layer 240 is not over-etched, as discussed below. Assume that the side-wall silicon oxide layer 240 is not over-etched, as shown in FIG. 51. This means that the side-wall silicon oxide layer 240 is formed in such a manner that it extends as far as a position facing the corner portions 260.
The gate electrode 238, the side-wall silicon oxide layer 240, and the field oxide layer 234 are used as a mask to implant ions into the main surface of the silicon substrate 230, to form the n+-type regions 244 as shown in FIG. 52. Sputtering is then used to form the titanium layer 246 over the entire main surface of the silicon substrate 230, so as to cover the gate electrode 238.
The titanium layer is subjected to thermal treatment to form the titanium silicide layers 248 and 250 on top of the upper surface of the gate electrode 238 and the n+-type regions 244, as shown in FIG. 53. The unreacted titanium layer that is positioned on top of the field oxide layer 234 and the side-wall silicon oxide layer 240 is then removed. The side-wall silicon oxide layer 240 is thus formed as far as a position corresponding to the corner portions 260 of the gate electrode 238. Thus the side surfaces of the gate electrode 238 are not exposed in the vicinity of the corner portions 260 of the gate electrode 238. This means that no silicon is supplied from the side surfaces of the gate electrode 238 in the vicinity of the corner portions 260, and thus the titanium layer does not react excessively with silicon at the corner portions 260. For that reason, the thickness of the edge portions of the titanium silicide layer 248 is not greater than the thickness of the central portion thereof. This prevents the problem of the creation of protuberant portions in the intermediary insulation layer, caused by increased thickness at the edge portions of the titanium silicide layer 248. However, other problems occur, as discussed below.
A partial plan view of the structure of FIG. 53 is shown in FIG. 54. Silicon comprised within the side-wall silicon oxide layer 240 links with the titanium layer, with the result that titanium silicide is formed in various places on the surface of the side-wall silicon oxide layer 240. Of this titanium silicide, links are created with the titanium silicide formed in the titanium silicide layer 248 and the side-wall silicon oxide layer 240, at the boundary between the titanium silicide layer 248 and the side-wall silicon oxide layer 240. As a result, the side portions of the titanium silicide layer 248 have a jagged form. For the same reason, side portions of a titanium silicide layer 250 also have a jagged form. Electrostatic charges can readily short-circuit at the points of this jagged form, which may cause deterioration in the characteristics of the MIS field-effect transistor.
The present invention was devised in order to solve the above described technical problems. The present invention addresses the above technical problems by providing a method of fabricating a semiconductor device comprising a MIS field-effect transistor having a lightly doped drain (LDD) structure, in which the edge portions of the gate insulation layer are not damaged, as well as a semiconductor device comprising a MIS field-effect transistor that is fabricated by this method.
Another technical problem is addressed by the present invention by providing a method of fabricating a semiconductor device comprising a MIS field-effect transistor whereby the thickness of edge portions of a silicide layer can be made the same as the thickness of a central portion thereof during the formation of the silicide layer on a gate electrode, as well as a semiconductor device comprising a MIS field-effect transistor that is fabricated by this method.
A yet further technical problem is addressed by the present invention by providing a method of fabricating a semiconductor device comprising a MIS field-effect transistor whereby edge portions of the silicide layer can be prevented from adopting a jagged form, as well as a semiconductor device comprising a MIS field-effect transistor that is fabricated by this method.
A first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention relates to a method of fabricating a semiconductor device comprising a MIS field-effect transistor, the MIS field-effect transistor including:
a semiconductor substrate having a main surface;
a gate insulation layer formed on the main surface and having a side surface;
a gate electrode formed on the gate insulation layer and having a corner portion between a side surface and an upper surface thereof; and
a pair of source/drain having a low-density impurity region and a high-density impurity region formed in the main surface.
This method comprises:
a step of forming the gate insulation layer and the gate electrode on the main surface;
a step of forming a protection layer for gate insulation layer comprising at least one of a silicon nitride film, a non-doped polysilicon film, and a non-doped amorphous silicon film, the protection layer for gate insulation layer being formed so as to shield the side surface of the gate insulation layer;
a step of forming a side-wall insulation layer comprising an impurity, in such a manner that the protection layer for gate insulation layer is sandwiched between the side-wall insulation layer and the side surface of the gate electrode; and
a step of forming the high-density impurity region in the main surface, then diffusing the impurity within the side-wall insulation layer by thermal diffusion into the main surface below the side-wall insulation layer to form the low-density impurity region in the main surface.
In this first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer is formed before the low-density impurity region is formed. During the diffusion of the impurity within the side-wall insulation layer into the main surface below the side-wall insulation layer by thermal diffusion, the impurity is prevented from passing through the side surface of the gate insulation layer and diffusing into the edge portions of the gate insulation layer. This is because the film quality of the silicon nitride film, non-doped polysilicon film, or non-doped amorphous silicon film forming the protection layer for gate insulation layer is extremely fine, so that it is difficult for the impurity to pass through the protection layer for gate insulation layer. Since it is also difficult for moisture or oxygen to pass through such films, it is possible to prevent moisture and oxygen from damaging the edge portions of the gate insulation layer. Of these three types of film, a silicon nitride film is the most effective. In addition, it is harder to etch silicon nitride film than to etch silicon oxide film.
As previously described, the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention makes it possible to prevent damage to the gate insulation layer caused by factors such as impurities, moisture, and oxygen. It is therefore possible to prevent changes in the characteristics of the semiconductor device comprising a MIS field-effect transistor and deterioration of the long-term reliability thereof, caused by damage to the gate insulation layer.
In a preferred configuration of the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming the protection layer for gate insulation layer comprises:
a step of forming a film that will become the protection layer for gate insulation layer on the main surface, so as to cover the gate insulation layer and the gate electrode; and
a step of anisotropically etching the film to form the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion and over positions corresponding to the side surface of the gate insulation layer.
In another preferred configuration of the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming a side-wall insulation layer comprises a step of forming the side-wall insulation layer so as to extend as far as a position corresponding to the corner portion.
In yet another preferred configuration of the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming a side-wall insulation layer comprises a step of over-etching the side-wall insulation layer to form the side-wall insulation layer to be positioned lower than the corner portion.
In still another preferred configuration of the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, after the step of forming the low-density impurity region and the high-density impurity region, the method further comprises: a step of forming a refractory metal layer so as to cover the side-wall insulation layer and the gate electrode; and a step of thermal treating the refractory metal layer to form a silicide layer on the upper surface of the gate electrode. When this aspect of the invention is combined with a step of forming the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion of the gate electrode and over positions corresponding to the side surface of the gate insulation layer, a protection layer for gate insulation layer can be formed between the silicide layer and the side-wall insulation layer. The presence of this protection layer for gate insulation layer makes it possible to prevent the occurrence of jagged portions in the boundary surface between the silicide layer and the side-wall insulation layer. It is therefore possible to prevent deterioration in the characteristics of the semiconductor device comprising a MIS field-effect transistor, caused by short-circuiting of electrostatic charges at such jagged portions.
When this aspect of the invention is combined with a step of forming the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion of the gate electrode and over positions corresponding to the side surface of the gate insulation layer, and also with a step of over-etching the side-wall insulation layer to form the side-wall insulation layer so that it is positioned lower than the corner portion, the thickness of the edge portions of the silicide layer will not become greater than the thickness of the central portion thereof. This is because the presence of the protection layer for gate insulation layer at a position corresponding to the corner portion of the gate electrode will ensure that the refractory metal layer does not form the silicide at the side surface of the gate electrode during the formation of the silicide layer. Thermal stresses in the silicide layer are greater when the thickness thereof is large comparing with when the thickness is small. This configuration ensures that the thickness of the edge portions of the silicide layer can be made smaller, so that the thermal stresses generated in the silicide layer can be reduced. This makes it possible to reduce the thermal stresses given to the gate insulation layer from the silicide layer. It is therefore possible to prevent changes in the characteristics of the semiconductor device comprising a MIS field-effect transistor and deterioration of the long-term reliability thereof.
In addition, since the thickness of the edge portions of the silicide layer is substantially the same as the thickness of the central portion thereof, the silicide layer is flat. This is reflected in the intermediary insulation layer positioned above the silicide layer, to be also flat. This makes it possible to avoid problems such as breaks in the wires of the wiring layer when the wiring layer is formed on top of the intermediary insulation layer positioned above the silicide layer.
The refractory metal layer preferably comprises at least one metal selected from the group of: titanium, cobalt, molybdenum, platinum, nickel, and tungsten.
In a further preferred configuration of the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the refractory metal layer comprises titanium. The step of forming the silicide layer may comprise:
a step of thermal treating the refractory metal layer to form a titanium silicide layer on the upper surface of the gate electrode;
a step of removing the refractory metal layer on the side-wall insulation layer; and
a step of thermal treating the titanium silicide layer to lower the resistance of the titanium silicide layer.
The refractory metal layer preferably comprises titanium. The initial thermal treatment ensures that the crystalline structure of the titanium silicide layer is C49. During this time, thermal stresses occur in the titanium silicide layer. These thermal stresses have an adverse effect on the gate insulation layer. The subsequent thermal treatment ensures that the crystalline structure of the silicide layer becomes C54. This processing is used because a C54 titanium silicide layer has a lower electrical resistance than a C49 titanium silicide layer. During this processing too, thermal stresses occur in the titanium silicide layer. Thus the gate insulation layer experiences thermal stresses twice. Since the thickness of the edge portions of the titanium silicide layer can be made smaller with this configuration, the thermal stresses experienced twice by the gate insulation layer can be reduced.
In a still further preferred configuration of the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the method further comprises a step of forming an oxide insulation layer by thermal oxidation so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode, between the step of forming the gate electrode and the step of forming the protection layer for gate insulation layer.
Since the protection layer for gate insulation layer has a dielectric constant that is higher than that of the oxide insulation layer, very small currents can easily flow in the surfaces thereof. Thus, if the protection layer for gate insulation layer is in direct contact with the gate electrode, the parasitic capacitance of the gate electrode will become large. This impedes the high speed operation of a semiconductor device comprising such a MIS field-effect transistor. In addition, a leakage current is generated from the gate electrode, through the protection layer for gate insulation layer, to the semiconductor substrate. This leakage current causes an increase in the current consumption of a semiconductor device comprising such a MIS field-effect transistor. With this configuration, the oxide insulation layer is formed so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode, so these problems can be solved. Note that if the gate electrode is formed of polysilicon or a silicide, the oxide insulation layer will be a silicon oxide layer.
Note also that if the oxide insulation layer is formed in such a manner that the thickness thereof is less than the thickness of the gate insulation layer, and it extends as far as on the low-density impurity region, the protection layer for gate insulation layer will be positioned above the oxide insulation layer above the low-density impurity region. Thus the protection layer for gate insulation layer is not formed so as to shield the entire side surface of the gate insulation layer, but to shield only part of that side surface. Even in this case too, it has a protective effect on the gate insulation layer. It should be noted, however, that the protective effect on the gate insulation layer is greater when the protection layer for gate insulation layer is formed so as to shield the entire side surface of the gate insulation layer.
In the first aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer comprises a silicon oxide layer, and the impurity therein is preferably at least one of phosphorus and boron.
A second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention relates to a method of fabricating a semiconductor device comprising a MIS field-effect transistor, the MIS field-effect transistor including:
a semiconductor substrate having a main surface;
a gate insulation layer formed on the main surface and having a side surface;
a gate electrode formed on the gate insulation layer and having a corner portion between a side surface and an upper surface thereof; and
a pair of source/drain having a low-density impurity region and a high-density impurity region formed in the main surface.
This method comprises:
a step of forming the gate insulation layer and the gate electrode on the main surface;
a step of forming a protection layer for gate insulation layer comprising at least one of a silicon nitride film, a non-doped polysilicon film, and a non-doped amorphous silicon film, the protection layer for gate insulation layer being formed so as to shield the side surface of the gate insulation layer;
a step of forming the low-density impurity region in the main surface;
a step of forming a side-wall insulation layer in such a manner that the protection layer for gate insulation layer is sandwiched between the side-wall insulation layer and the side surface of the gate electrode; and
a step of forming the high-density impurity region in the main surface.
In this second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer is formed before the low-density impurity region is formed. When the low-density impurity region is formed by thermal diffusion or ion implantation, the impurity or ions can be prevented from penetrating the edge portion of the gate insulation layer through the side surface of the gate insulation layer. This is because the film quality of the silicon nitride film, non-doped polysilicon film, or non-doped amorphous silicon film forming the protection layer for gate insulation layer is extremely fine, so that it is difficult for the impurity or ions to pass through the protection layer for gate insulation layer. Since it is also difficult for moisture or oxygen to pass through such films, it is possible to prevent moisture and oxygen from damaging the edge portions of the gate insulation layer. Of these three types of film, a silicon nitride film is the most effective. In addition, it is harder to etch silicon nitride film than to etch silicon oxide film.
As previously described, the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention makes it possible to prevent damage to the gate insulation layer due to causes such as impurities, ions, moisture, and oxygen. It is therefore possible to prevent changes in the characteristics of the semiconductor device comprising a MIS field-effect transistor and deterioration of the long-term reliability thereof, caused by damage to the gate insulation layer.
In a preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming the protection layer for gate insulation layer comprises:
a step of forming a film that will become the protection layer for gate insulation layer on the main surface, so as to cover the gate insulation layer and the gate electrode; and
a step of anisotropically etching the film to form the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion and over positions corresponding to the side surface of the gate insulation layer.
In another preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming a side-wall insulation layer comprises a step of forming the side-wall insulation layer so as to extend as far as a position corresponding to the corner portion.
In still another preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming a side-wall insulation layer comprises a step of over-etching the side-wall insulation layer to form the side-wall insulation layer to be positioned lower than the corner portion.
In yet another preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, after the step of forming the high-density impurity region, the method further comprises:
a step of forming a refractory metal layer so as to cover the side-wall insulation layer and the gate electrode; and
a step of thermal treating the refractory metal layer to form a silicide layer on the upper surface of the gate electrode.
When this aspect of the invention is combined with a step of forming the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion of the gate electrode and over positions corresponding to the side surface of the gate insulation layer, the protection layer for gate insulation layer can be formed between the silicide layer and the side-wall insulation layer. The presence of this protection layer for gate insulation layer makes it possible to prevent the occurrence of jagged portions in the boundary surface between the silicide layer and the side-wall insulation layer.
When this aspect of the invention is combined with a step of forming the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion of the gate electrode and over positions corresponding to the side surface of the gate insulation layer, and a step of over-etching the side-wall insulation layer to form the side-wall insulation layer so that it is positioned lower than the corner portion, the thickness of the edge portions of the silicide layer will not become greater than the thickness of the central portion thereof. This is because the presence of the protection layer for gate insulation layer at a position corresponding to the corner portion of the gate electrode will ensure that the refractory metal layer does not form the silicide at the side surface of the gate electrode during the formation of the silicide layer. Thermal stresses in the silicide layer are greater when the thickness thereof is large comparing with when the thickness is small. This configuration ensures that the thickness of the edge portions of the silicide layer can be made smaller, so that the thermal stresses generated in the silicide layer can be reduced. This makes it possible to reduce the thermal stresses given to the gate insulation layer from the silicide layer.
In addition, since the thickness of the edge portions of the silicide layer is the same as the thickness of the central portion thereof, the silicide layer is flat. This is reflected in the intermediary insulation layer positioned above the silicide layer, to be also flat. This makes it possible to avoid problems such as breaks in the wires of the wiring layer when the wiring layer is formed on top of the intermediary insulation layer positioned above the silicide layer.
The refractory metal layer preferably comprises at least one metal selected from the group of: titanium, cobalt, molybdenum, platinum, nickel, and tungsten.
In a further preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the refractory metal layer comprises titanium. The step of forming a silicide layer may comprise:
a step of thermal treating the refractory metal layer to form a titanium silicide layer on the upper surface of the gate electrode;
a step of removing the refractory metal layer on the side-wall insulation layer; and
a step of thermal treating the titanium silicide layer to lower the resistance of the titanium silicide layer.
The refractory metal layer preferably comprises titanium. The initial thermal treatment ensures that the crystalline structure of the titanium silicide layer is C49. During this time, thermal stresses occur in the titanium silicide layer. These thermal stresses have an adverse effect on the gate insulation layer. The subsequent thermal treatment ensures that the crystalline structure of the silicide layer becomes C54. This processing is used because a C54 titanium silicide layer has a lower electrical resistance than a C49 titanium silicide layer. During this processing too, thermal stresses occur in the titanium silicide layer. Thus the gate insulation layer experiences thermal stresses twice. Since the thickness of the edge portions of the titanium silicide layer can be made smaller with this configuration, the thermal stresses experienced twice by the gate insulation layer can be reduced.
In a still further preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming the low-density impurity region comprises a step of implanting ions of an impurity obliquely into the main surface. This tilted ion implantation is a method of implanting ions at a constant angle with respect to the main surface of the semiconductor substrate.
If there is no protection layer for gate insulation layer when tilted ion implantation is used to form the low-density impurity region, the ions would strike the side surface of the gate insulation layer directly. This would make it easy for a large number of breaks to occur in the crystalline structure at the edge portions of the gate insulation layer. Since this configuration provides the protection layer for gate insulation layer, the ions can be prevented from striking the side surfaces of the gate insulation layer directly.
In a yet further preferred configuration of the second aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, between the step of forming the gate electrode and the step of forming the protection layer for gate insulation layer, the method further comprises a step of forming an oxide insulation layer by thermal oxidation so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode.
Since the protection layer for gate insulation layer has a dielectric constant that is higher than that of the oxide insulation layer, very small currents can easily flow in the surfaces thereof. Thus, if the protection layer for gate insulation layer is in direct contact with the gate electrode, the parasitic capacitance of the gate electrode will become large. This impedes the high speed operation of a semiconductor device comprising such a MIS field-effect transistor. In addition, a leakage current is generated from the gate electrode, through the protection layer for gate insulation layer, to the semiconductor substrate. This leakage current causes an increase in the current consumption of a semiconductor device comprising such a MIS field-effect transistor. With this configuration, the oxide insulation layer is formed so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode, so these problems can be solved. Note that if the gate electrode is formed of polysilicon or a silicide, the oxide insulation layer will be a silicon oxide layer.
Note also that if the oxide insulation layer is formed in such a manner that the thickness thereof is less than the thickness of the gate insulation layer, and it extends as far as on the low-density region, the protection layer for gate insulation layer will be positioned above the oxide insulation layer above the low-density impurity region. Thus the protection layer for gate insulation layer is not formed so as to shield the entire side surface of the gate insulation layer, but to shield only part of that side surface. In this case too, it has a protective effect on the gate insulation layer. It should be noted, however, that the protective effect on the gate insulation layer is greater when the protection layer for gate insulation layer is formed to shield the entire side surface of the gate insulation layer.
A third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention relates to a method of fabricating a semiconductor device comprising a MIS field-effect transistor, the MIS field-effect transistor including:
a semiconductor substrate having a main surface;
a gate insulation layer formed on the main surface and having a side surface;
a gate electrode formed on the gate insulation layer and having a corner portion between a side surface and an upper surface thereof; and
a pair of source/drain formed in the main surface.
This method comprises:
a step of forming the gate insulation layer and the gate electrode on the main surface;
a step of forming a protection layer for gate insulation layer comprising at least one of a silicon nitride film, a non-doped polysilicon film, and a non-doped amorphous silicon film, the protection layer for gate insulation layer being formed so as to shield the side surface of the gate insulation layer;
a step of forming a side-wall insulation layer in such a manner that the protection layer for gate insulation layer is sandwiched between the side-wall insulation layer and the side surface of the gate electrode;
a step of forming the pair of source/drain in the main surface;
a step of forming a refractory metal layer so as to cover the side-wall insulation layer and the gate electrode; and
a step of thermal treating the refractory metal layer to form a silicide layer on the upper surface of the gate electrode.
In this third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer is formed before the pair of source/drain is formed. When the pair of source/drain is formed by thermal diffusion or ion implantation, the impurity or ions can be prevented from penetrating the edge portion of the gate insulation layer through the side surface of the gate insulation layer. This is because the film quality of the silicon nitride film, non-doped polysilicon film, or non-doped amorphous silicon film forming the protection layer for gate insulation layer is extremely fine, so that it is difficult for the impurity or ions to pass through the protection layer for gate insulation layer. Since it is also difficult for moisture or oxygen to pass through such films, it is possible to prevent moisture and oxygen from damaging the edge portions of the gate insulation layer. Of these three types of film, a silicon nitride film is the most effective. In addition, it is harder to etch silicon nitride film than to etch silicon oxide film.
As previously described, the third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention makes it possible to prevent damage to the gate insulation layer due to causes such as impurities, ions, moisture, and oxygen. It is therefore possible to prevent changes in the characteristics of the semiconductor device comprising a MIS field-effect transistor and deterioration of the long-term reliability thereof, caused by damage to the gate insulation layer.
In a preferred configuration of the third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming the protection layer for gate insulation layer comprises:
a step of forming a film that will become the protection layer for gate insulation layer on the main surface, so as to cover the gate insulation layer and the gate electrode; and
a step of anisotropically etching the film to form the protection layer for gate insulation layer so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion and over positions corresponding to the side surface of the gate insulation layer. With this configuration, a protection layer for gate insulation layer can be formed between the silicide layer and the side-wall insulation layer. The presence of this protection layer for gate insulation layer makes it possible to prevent the occurrence of jagged portions in the boundary surface between the silicide layer and the side-wall insulation layer.
In another preferred configuration of the third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming a side-wall insulation layer comprises a step of forming the side-wall insulation layer so as to extend as far as a position corresponding to the corner portion.
In yet another preferred configuration of the third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the step of forming a side-wall insulation layer comprises a step of over-etching the side-wall insulation layer to form the side-wall insulation layer to be positioned lower than the corner portion.
With this configuration, the side-wall insulation layer is over-etched but the thickness of the edge portions of the silicide layer will not become greater than the thickness of the central portion thereof. This is because the presence of the protection layer for gate insulation layer at a position corresponding to the corner portion of the gate electrode will ensure that the refractory metal layer does not form the silicide at the side surface of the gate electrode during the formation of the silicide layer. Thermal stresses in the silicide layer are greater when the thickness thereof is large comparing with when the thickness is small. This configuration ensures that the thickness of the edge portions of the silicide layer can be made smaller, so that the thermal stresses generated in the silicide layer can be reduced. This makes it possible to reduce the thermal stresses given to the gate insulation layer from the silicide layer.
In addition, since the thickness of the edge portions of the silicide layer is the same as the thickness of the central portion thereof, the silicide layer is flat. This is reflected in the intermediary insulation layer positioned above the silicide layer, to be also flat. This makes it possible to avoid problems such as breaks in the wires of the wiring layer when the wiring layer is formed on top of the intermediary insulation layer positioned above the silicide layer.
The refractory metal layer preferably comprises at least one metal selected from the group of: titanium, cobalt, molybdenum, platinum, nickel, and tungsten.
In a further preferred configuration of the third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the refractory metal layer comprises a titanium. The step of forming the silicide layer may comprise:
a step of thermal treating the refractory metal layer to form a titanium silicide layer in the upper surface of the gate electrode;
a step of removing the refractory metal layer on the side-wall insulation layer; and
a step of thermal treating the titanium silicide layer to lower the resistance of the titanium silicide layer.
The refractory metal layer preferably comprises titanium. The initial thermal treatment ensures that the crystalline structure of the titanium silicide layer is C49. During this time, thermal stresses occur in the titanium silicide layer. These thermal stresses have an adverse effect on the gate insulation layer. The subsequent thermal treatment ensures that the crystalline structure of the silicide layer becomes C54. This processing is used because a C54 titanium silicide layer has a lower electrical resistance than a C49 titanium silicide layer. During this processing too, thermal stresses occur in the titanium silicide layer. Thus the gate insulation layer experiences thermal stresses twice. Since the thickness of the edge portions of the titanium silicide layer can be made smaller with this configuration, the thermal stresses experienced twice by the gate insulation layer can be reduced.
In still another preferred configuration of the third aspect of the method of fabricating a semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, between the step of forming the gate electrode and the step of forming the protection layer for gate insulation layer, the method further comprises a step of forming an oxide insulation layer by thermal oxidation so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode.
Since the protection layer for gate insulation layer has a dielectric constant that is higher than that of the oxide insulation layer, very small currents can easily flow in the surfaces thereof. Thus, if the protection layer for gate insulation layer is in direct contact with the gate electrode, the parasitic capacitance of the gate electrode will become large. This impedes the high speed operation of a semiconductor device comprising such a MIS field-effect transistor. In addition, a leakage current is generated from the gate electrode, through the protection layer for gate insulation layer, to the semiconductor substrate. This leakage current causes an increase in the current consumption of a semiconductor device comprising such a MIS field-effect transistor. With this configuration, the oxide insulation layer is formed so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode, so these problems can be solved. Note that if the gate electrode is formed of polysilicon or a silicide, the oxide insulation layer will be a silicon oxide layer.
Note also that if the oxide insulation layer is formed in such a manner that the thickness thereof is less than the thickness of the gate insulation layer, and it extends as far as above the pair of source/drain, the protection layer for gate insulation layer is positioned above the oxide insulation layer which is above the pair of source/drain. Thus the protection layer for gate insulation layer is not formed so as to shield the entire side surface of the gate insulation layer, but to shield only part of that side surface. In this case too, it has a protective effect on the gate insulation layer. It should be noted, however, that the protective effect on the gate insulation layer is greater when the protection layer for gate insulation layer is formed to shield the entire side surface of the gate insulation layer.
A first aspect of a semiconductor device comprising a MIS field-effect transistor, the MIS field-effect transistor including:
a semiconductor substrate having a main surface;
a gate insulation layer formed on the main surface and having a side surface;
a gate electrode formed on the gate insulation layer and having a corner portion between a side surface and an upper surface thereof;
a pair of source/drain formed in the main surface;
a protection layer for gate insulation layer comprising at least one of a silicon nitride film, a non-doped polysilicon film, and a non-doped amorphous silicon film, the protection layer for gate insulation layer being formed so as to shield the side surface of the gate insulation layer;
a side-wall insulation layer formed in such a manner that the protection layer for gate insulation layer is sandwiched between the side-wall insulation layer and the side surface of the gate electrode; and
a silicide layer formed on the upper surface of the gate electrode.
In a preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer is formed so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion over positions corresponding to the side surface of the gate insulation layer.
With this configuration, the protection layer for gate insulation layer is provided between the silicide layer and the side-wall insulation layer. The presence of this protection layer for gate insulation layer makes it possible to prevent the occurrence of jagged portions in the boundary surface between the silicide layer and the side-wall insulation layer.
In another preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer is formed so as to extend as far as a position corresponding to the corner portion.
In still another preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer is formed to be positioned lower than the corner portion. If this configuration is combined with the configuration in which the protection layer for gate insulation layer is formed so as to shield the side surface of the gate electrode and the side surface of the gate insulation layer from a position corresponding to the corner portion over positions corresponding to the side surface of the gate insulation layer, the thickness of the edge portions of the silicide layer will not become greater than the thickness of the central portion thereof. This is because the presence of the protection layer for gate insulation layer at a position corresponding to the corner portion of the gate electrode will ensure that the refractory metal layer does not form the silicide at the side surface of the gate electrode during the formation of the silicide layer. Thermal stresses in the silicide layer are greater when the thickness thereof is large comparing with when the thickness is small. This configuration ensures that the thickness of the edge portions of the silicide layer can be made smaller, so that the thermal stresses generated in the silicide layer can be reduced. This makes it possible to reduce the thermal stresses given to the gate insulation layer from the silicide layer.
In addition, since the thickness of the edge portions of the silicide layer is the same as the thickness of the central portion thereof, the silicide layer is flat. This is reflected in the intermediary insulation layer positioned above the silicide layer, to be also flat. This makes it possible to avoid problems such as breaks in the wires of the wiring layer when the wiring layer is formed on top of the intermediary insulation layer positioned above the silicide layer.
In a further preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the pair of source/drain comprises a low-density impurity region and a high-density impurity region formed in the main surface.
Yet another preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention further comprises an oxide insulation layer positioned between the gate electrode and the protection layer for gate insulation layer and formed so as to cover the side surface of the gate electrode and the side surface of the gate insulation layer. Since the protection layer for gate insulation layer has a dielectric constant that is higher than that of the oxide insulation layer, very small currents can easily flow in the surfaces thereof. Thus, if the protection layer for gate insulation layer is in direct contact with the gate electrode, the parasitic capacitance of the gate electrode will become large. This impedes the high speed operation of a semiconductor device comprising such a MIS field-effect transistor. In addition, a leakage current is generated from the gate electrode, through the protection layer for gate insulation layer, to the silicon substrate. This leakage current causes an increase in the current consumption of a semiconductor device comprising such a MIS field-effect transistor. With this configuration, the oxide insulation layer is formed so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode, so these problems can be solved. Note that if the gate electrode is formed of polysilicon or a silicide, the oxide insulation layer will be a silicon oxide layer.
In a still further preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the oxide insulation layer is formed so that the thickness thereof is less than the thickness of the gate insulation layer and it also extends as far as on the pair of source/drain. The protection layer for gate insulation layer is positioned on the oxide insulation layer which is on the pair of source/drain.
In a yet further preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer has a thickness that is greater than or equal to 2 nm but less than 10 nm. This thickness is made to be greater than or equal to 2 nm because it is thought that if the thickness of the protection layer for gate insulation layer is smaller than this value, it will not fulfill the role of protecting the gate insulation layer. The technique disclosed in Japanese Patent Application Laid-Open No. 9-162402 sets the thickness of the silicon nitride layer to 10 nm. With the technique disclosed in that document, it is thought to be difficult to make the thickness of a silicon nitride layer less than 10 nm. That is to say, the nxe2x88x92-type regions 214 are formed directly under the silicon nitride layer 210 in FIG. 42. If the thickness of the silicon nitride layer 210 is less than 10 nm, it is thought that the nxe2x88x92-type regions 214 will be absorbed into the n-type region 218. With the configuration of the invention, no such independent impurity region is formed below the protection layer for gate insulation layer, so that the thickness of the protection layer for gate insulation layer can be made less than 10 nm.
In an even further preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer includes a silicon oxide layer comprising at least one of phosphorus and boron.
In a final preferred configuration of the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the pair of source/drain is provided with an edge portion such that the edge portion is at a position that overlaps the gate electrode.
A second aspect of a semiconductor device comprising a MIS field-effect transistor, the MIS field-effect transistor including:
a semiconductor substrate having a main surface;
a gate insulation layer formed on the main surface and having a side surface;
a gate electrode formed on the gate insulation layer and having a corner portion between a side surface and an upper surface thereof;
a pair of source/drain formed in the main surface; and
a protection layer for gate insulation layer having a thickness that is greater than or equal to 2 nm but less than 10 nm, that is formed so as to shield the side surface of the gate insulation layer and comprises at least one of a silicon nitride film, a non-doped polysilicon film, and a non-doped amorphous silicon film.
In the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer has a thickness that is greater than or equal to 2 nm but less than 10 nm. The reasons for this are the same as the numerical limitations described above with respect to the first aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention. A preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention further comprises an oxide insulation layer positioned between the gate electrode and the protection layer for gate insulation layer and formed to cover the side surface of the gate electrode and the side surface of the gate insulation layer. Since the protection layer for gate insulation layer has a dielectric constant that is higher than that of the oxide insulation layer, very small currents can easily flow in the surfaces thereof. Thus, if the protection layer for gate insulation layer is in direct contact with the gate electrode, the parasitic capacitance of the gate electrode will become large. This impedes the high speed operation of a semiconductor device comprising such a MIS field-effect transistor. In addition, a leakage current is generated from the gate electrode, through the protection layer for gate insulation layer, to the silicon substrate. This leakage current causes an increase in the current consumption of a semiconductor device comprising such a MIS field-effect transistor. With this configuration, the oxide insulation layer is formed so as to cover the side surface of the gate insulation layer and the side surface of the gate electrode, so these problems can be solved. Note that if the gate electrode is formed of polysilicon or a silicide, the oxide insulation layer will be a silicon oxide layer.
In another preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the oxide insulation layer is formed so that the thickness thereof is less than the thickness of the gate insulation layer and it also extends as far as on the pair of source/drain. The protection layer for gate insulation layer may be positioned above the oxide insulation layer which is above the pair of source/drain.
Yet another preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention further comprises: a side-wall insulation layer formed in such a manner that the protection layer for gate insulation layer is sandwiched between the side-wall insulation layer and the side surface of the gate electrode.
In still another preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the pair of source/drain comprises a low-density impurity region and a high-density impurity region. In a further preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the protection layer for gate insulation layer is formed to extend from a position corresponding to the corner portion and over positions corresponding to the side surface of the gate insulation layer. In a yet further preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer is formed so as to extend as far as a position corresponding to the corner portion. In an even further preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer is formed to be positioned lower than the corner portion.
A still further preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention also comprises a silicide layer formed on the upper surface of the gate electrode. If this configuration is combined with a configuration in which the protection layer for gate insulation layer is formed to extend from a position corresponding to the corner portion and over positions corresponding to the side surface of the gate insulation layer, the protection layer for gate insulation layer lies between the silicide layer and the side-wall insulation layer. The presence of this protection layer for gate insulation layer makes it possible to prevent the occurrence of jagged portions in the boundary surface between the silicide layer and the side-wall insulation layer. Furthermore, if this configuration is combined with the configuration in which the protection layer for gate insulation layer is formed to extend from a position corresponding to the corner portion and over positions corresponding to the side surface of the gate insulation layer, and also with a configuration in which the side-wall insulation layer is formed so as to be positioned lower than the corner portion, the thickness of the edge portions of the silicide layer will not become greater than the thickness of the central portion thereof. This is because the presence of the protection layer for gate insulation layer at a position corresponding to the corner portion of the gate electrode will ensure that the refractory metal layer does not form the silicide at the side surface of the gate electrode during the formation of the silicide layer. Thermal stresses in the silicide layer are greater when the thickness thereof is large comparing with when the thickness is small. Since the thickness of the edge portions of the silicide layer can be made smaller, the thermal stresses generated in the silicide layer can be reduced. This ensures that the thermal stresses acting on the gate insulation layer can also be reduced. In addition, since the thickness of the edge portions of the silicide layer is the same as the thickness of the central portion thereof, the silicide layer is flat. This is reflected in the intermediary insulation layer positioned above the silicide layer, to be also flat. This makes it possible to avoid problems such as breaks in the wires of the wiring layer when the wiring layer is formed on top of the intermediary insulation layer positioned above the silicide layer.
In yet another preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the pair of source/drain is provided with an edge portion such that the edge portion is at a position that overlaps the gate electrode. In a final preferred configuration of the second aspect of the semiconductor device comprising a MIS field-effect transistor in accordance with the present invention, the side-wall insulation layer comprises a silicon oxide layer comprising at least one of phosphorus and boron.
The material of the gate insulation layer of the present invention could be a silicon oxide film, a SiON film, or a tantalum oxide film. The low-density impurity region and the high-density impurity region could be of an LDD structure, for example. The various aspects of the method of the present invention can be applied to making the protection layer for gate insulation layer have a thickness that is greater than or equal to 2 nm but less than 10 nm.
When a silicide is formed on the upper surface of the gate electrode by self-alignment in the present invention, it is necessary to fabricate at least the upper surface of the gate electrode of a material comprising silicon.
To achieve the effect of preventing excessive silicide reactions and also preventing the occurrence of electrostatic charges in the configuration of the upper surface of the gate electrode comprising a silicide, it is necessary to make the protection layer for gate insulation layer a silicon nitride layer.